The present invention relates to methods of fabricating semiconductor materials used in electronic devices, such as power electronic devices. In particular, some embodiments of the invention relate to processes that can reduce crystal defects in silicon carbide, and the resulting structures and devices. The present invention is related to the subject matter disclosed and claimed in co-pending and commonly assigned application Ser. No. 10/046,346; filed Oct. 26, 2001 and now published as No. 2003-0080842 A1 as well as co-pending and commonly assigned application Ser. No. 10/605,312 filed Sep. 22, 2003; the contents of both of which are incorporated entirely herein by reference in their entirety, as set forth fully herein.
Silicon Carbide
Silicon carbide (SiC) has emerged over the last two decades as an appropriate candidate semiconductor material that can offer a number of advantages over both silicon and gallium arsenide. In particular, silicon carbide has a wide bandgap, a high breakdown electric field, a high thermal conductivity, a high saturated electron drift velocity, and is physically extremely robust. Silicon carbide has an extremely high melting point and is one of the hardest known materials in the world.
Because of its physical properties, however, silicon carbide also may be relatively difficult to produce. Because silicon carbide can grow in many polytypes, it may be difficult to grow into large single crystals. The high temperatures used to grow silicon carbide also may make control of impurity levels (including doping) relatively difficult, and likewise may raise difficulties in the production of thin films (e.g. epitaxial layers). Because of its hardness, the traditional steps of slicing and polishing semiconductor wafers also may be more difficult with silicon carbide. Similarly, its resistance to chemical attack may make it difficult to etch in a conventional fashion.
In addition, silicon carbide can form over 150 polytypes, many of which are separated by relatively small thermodynamic differences. As a result, growing single crystal substrates and high quality epitaxial layers (“epilayers”) in silicon carbide has been, and may remain, a difficult task.
Nevertheless, based on a great deal of research and discovery in this particular field, including that carried out by the assignee of the present invention, a number of advances have been made in the growth of silicon carbide and its fabrication into useful devices. Accordingly, commercial devices are now available that incorporate silicon carbide as a substrate for other useful semiconductors such as the Group III nitrides, to produce blue and green light emitting diodes. Also, commercial silicon carbide-based devices are available for microwave and radio frequency (RF) high-power, high-voltage applications, and/or for other applications.
As the success of silicon-carbide technology has increased the availability of certain SiC-based devices, particular aspects of those devices have become more apparent. In particular, it has been observed that the forward voltage (Vf) of some silicon carbide-based bipolar devices such as bipolar power devices may increase noticeably during operation of some devices. This increase is generally referred to as “Vf drift.” For a number of reasons, such functional problems in semiconductor devices can often result from defects in the crystal structure of the material from which the devices are formed. Examples of these defects are discussed below.
Deposition systems and methods are commonly used to form layers of semiconductor materials, such as thin epitaxial films, on substrates. For example, a chemical vapor deposition (CVD) reactor system and process may be used to form a layer of semiconductor material such as silicon carbide (SiC) on a substrate. CVD processes may be particularly effective for forming layers with controlled properties, thicknesses, and/or arrangements such as epitaxial layers. Typically, in a deposition system, such as a CVD system, the substrate is placed in a reaction chamber within a susceptor and one or more process gases including reagents or reactants to be deposited on the substrate are introduced into the chamber adjacent the substrate. The process gases may be flowed through the reaction chamber in order to provide a uniform or controlled concentration of the reagents or reactants to the substrate.
Silicon Carbide Crystal Structure
A deposition system, such as a CVD reactor, may be used to form epitaxial layers of silicon carbide on a single crystal silicon carbide substrate having a predetermined polytype such as 2H, 4H, 6H, 15R, 3C and the like. The term “polytype” refers to the ordering and arrangement of layers of atoms within a crystal structure. Thus, although the different polytypes of silicon carbide are stoichiometrically identical, they possess different crystal structures and consequently may have different material properties such as bandgap, carrier mobility and breakdown field strength. The letters H, R and C refer to the general crystal structure of the polytype, namely, hexagonal, rhombohedral and cubic, respectively. The numbers in the polytype designations refer to the repetition period of layer arrangements. Thus, a 4H crystal has a hexagonal crystal structure in which the arrangement of atoms in a crystal repeats every four bi-layers.
FIG. 1 illustrates a hexagonal unit cell of a hypothetical crystal. The unit cell 60 includes a pair of opposing hexagonal faces 61A, 61B. The hexagonal faces are normal to the c-axis, which runs along the <0001> direction as defined by the Miller-Bravais indexing system for designating directions in a hexagonal crystal. Accordingly the hexagonal faces are sometimes called the c-faces, which define the c-planes or basal planes of the crystal. Planes perpendicular to the c-plane are referred to as prismatic planes.
Silicon carbide possesses a number of potentially advantageous physical and electronic characteristics for semiconductor performance and devices. These may include a wide bandgap, high thermal conductivity, high saturated electron drift velocity, high electron mobility, superior mechanical strength, and radiation hardness. However, the presence of crystalline defects in silicon carbide films may limit the performance of electronic devices fabricated in the films, depending on the type, location, and density of the defects. Accordingly, significant research has focused on reducing defects in silicon carbide films. Certain defects, such as micropipes, are known to severely limit and even prevent device performance. Other defects, such as threading dislocations, are not considered to be individually catastrophic to device operation, and therefore they may not significantly impact device performance at densities normally found in epitaxial films.
For applications where a high voltage blocking capability is desired (for example power switching applications), silicon carbide films are usually grown “off-axis.” That is, the substrate crystal is sliced at an angle that is slightly oblique to the normal crystal axis (the c-axis). Taking for example a hexagonal polytype such as 4H or 6H, the oblique angle of the cut may be made in one of the standard crystallographic directions illustrated in FIG. 2, namely the <11{overscore (2)}0> direction (towards a point of the hexagonal unit cell) or the <10{overscore (1)}0> direction (towards the center of a flat side of the hexagonal unit cell), or along a different direction. As a result of the off-axis slicing, the face of a prepared substrate may be characterized by a periodic arrangement of plateaus and steps. See, for example, U.S. Pat. No. 4,912,064 to Kong et al, entitled Homoepitaxial Growth of Alpha-SiC Thin Films and Semiconductor Devices Fabricated Thereon, assigned to North Carolina State University, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
Thus when an epitaxial layer is grown on the substrate, the deposited atoms bond to atoms at the exposed edges of the crystal layer steps, which causes the steps to grow laterally in so-called step-flow fashion. Step-flow growth is illustrated in FIG. 3. Each layer or step grows in the direction in which the crystal was originally cut off-axis (the <11{overscore (2)}0> direction in the case illustrated in FIG. 3).
Crystallographic Defects
At the most basic level, structural crystallographic defects may fall into four categories: point defects, line defects, planar defects and three dimensional defects. Point defects include vacancies, line defects include dislocations, planar defects include stacking faults and three-dimensional defects include polytype inclusions.
A dislocation is a kind of structural imperfection that extends for many unit cell lengths throughout a crystal. A more definite description of dislocation may classify them as screw and edge dislocations. As recognized by those persons skilled in this art, a symmetrical path followed from atom to atom (or from ion to ion) in a real crystal that returns upon itself, is referred to as a Burgers circuit. If the same path in the lattice that typifies the structure does not return upon itself, so that the beginning and end do not lie on the same atom, then the Burgers circuit encloses one or more dislocations. The vector that completes the closed circuit in the lattice is referred to as the Burgers vector and measures the magnitude and direction of the dislocation.
If the Burgers vector is parallel to the line that locates the dislocation, the defect is referred to as a screw dislocation. Alternatively, if the Burgers vector is perpendicular to the dislocation, it is referred to as an edge dislocation. The simplest version of an edge dislocation is an incomplete plane of atoms or ions interleaved between two normal planes in a manner somewhat analogous to an extra card inserted halfway into a deck.
Screw dislocations are not necessarily disadvantageous and, in fact, can be advantageous for the growth of a crystal. For example, a IC threading screw dislocation at the nominally (0001) oriented growth surface of a silicon carbide crystal presents a regenerating edge that is one or a few atoms high. At this edge, continued growth of the crystal is relatively easy. Dislocations, however, allow plastic flow to occur in a crystal relatively easily. Dislocations may move preferentially along slip planes. The dislocation moves relatively easily through the crystal because motion in the slipped plane involves only a slight displacement of the structural elements. Stated differently, the slipped planes provide a low-energy intermediate state by which a crystal can be reorganized.
Defects in Silicon Carbide
In silicon carbide power devices, the availability of such a relatively low-energy intermediate state may encourage faults to continue to grow, since the operation of the device can provide the relatively small amount of energy that may be required to drive dislocation motion.
Commercial quality SiC wafers and epilayers typically include both screw and edge dislocations. These dislocations can be further grouped by their alignment within the crystal. Those dislocations that propagate along the c-axis are called threading dislocations, while dislocations that lie within the c-plane are termed basal plane dislocations. In general, in SiC, it is energetically favorable that basal plane dislocations may preferentially decompose into partial dislocations via the mechanism described below:⅓<11{overscore (2)}0>→⅓<10{overscore (1)}0>+⅓<01{overscore (1)}0>  Equation 1
The above decomposition reaction describes the decomposition of a basal plane dislocation into two Shockley partial dislocations. The line defects generated during the above decomposition will bound a stacking fault defect. In fact, partial dislocations will generally bind the entire perimeter of the stacking fault unless the stacking fault reaches a free surface. This stacking fault will generally be electrically active in bipolar devices, and, during forward operation, the density of the electron-hole plasma may be reduced in the vicinity of the stacking fault. The reduced plasma density may increase the forward voltage of the device. A further potential complication is that through recombination enhanced dislocation glide, the stacking fault may continue to expand during forward operation of the device. This behavior can raise a substantial barrier to device exploitation because it can result in devices % with functional properties that can change unpredictably during operation.
Stated differently, the application of electric current through a silicon carbide bipolar device may tend to initiate or propagate (or both) changes in the crystal structure due to preexisting defects in the crystal. As noted above, many SiC polytypes are in close thermodynamic proximity, and solid phase transformations are quite possible. When the stacking faults impact a significant portion of the active area of a device, they tend to cause the forward voltage to increase in an undesirable manner that can prevent the device from operating as precisely and/or efficiently as required or desired in many applications.
In some conventions, dislocation density is described by centimeters of dislocation length per cubic centimeter of material, and thus report dislocation density units of per square centimeter (cm−2). In another convention (and as used herein) the off-axis orientation of 4H—SiC substrates for SiC epilayer growth and the common etch technique used to detect dislocations make it more convenient to use etch pit density (also in the units of cm−2), to describe dislocation densities in SiC. Those of skill in this art will thus recognize that for a given dislocation density expressed as cm/cm3, one could get a very different dislocation pit density when expressed as pits/cm2 depending on the typical dislocation configuration and the off-axis angle of the substrate. Therefore, although the two numbers will have the same net units (cm−2), they do not necessarily indicate the same actual dislocation density. For the sake of clarity and consistency, in the present application, dislocation density will be described as the density of specific pits delineated on an etched epi-surface of a silicon face prepared, 8° off-axis (0001) oriented substrate.
Present commercially available 4H—SiC substrates may have approximately 1E3 to 1E5 (about 103–105) dislocations per cm2 by the convention used herein. This includes threading screw and edge dislocations and basal plane dislocations. Presumably, all types of dislocations can impact device performance, but the basal plane dislocation has been particularly implicated as the prevalent nucleation site of the stacking faults that may cause Vf drift.
In turn, defects in the substrate are often replicated in epitaxial layers grown on such substrates, thus making substrate crystal quality a profoundly important factor with respect to the quality and performance of resulting devices.
Conventional substrate preparation and epilayer growth practices can fairly effectively reduce the density of basal plane dislocations from 1E3–1E4 cm−2 in the substrate to about 400 cm−2 in the epilayer. This reduction in dislocation density may be accomplished via changes in both the substrate preparation and the epilayer growth operations.
Accordingly, for continued improvement in the structure and operation of SiC-based bipolar and other devices it may be desirable to provide continued improvement in the underlying substrates and their crystal structures.